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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 | // SPDX-License-Identifier: GPL-2.0 /* * Copyright (c) 2018, The Linux Foundation. All rights reserved. */ /* * In Certain QCOM SoCs like apq8096 and msm8996 that have KRYO processors, * the CPU frequency subset and voltage value of each OPP varies * based on the silicon variant in use. Qualcomm Process Voltage Scaling Tables * defines the voltage and frequency value based on the msm-id in SMEM * and speedbin blown in the efuse combination. * The qcom-cpufreq-nvmem driver reads the msm-id and efuse value from the SoC * to provide the OPP framework with required information. * This is used to determine the voltage and frequency value for each OPP of * operating-points-v2 table when it is parsed by the OPP framework. */ #include <linux/cpu.h> #include <linux/err.h> #include <linux/init.h> #include <linux/kernel.h> #include <linux/module.h> #include <linux/nvmem-consumer.h> #include <linux/of.h> #include <linux/of_device.h> #include <linux/platform_device.h> #include <linux/pm_domain.h> #include <linux/pm_opp.h> #include <linux/slab.h> #include <linux/soc/qcom/smem.h> #define MSM_ID_SMEM 137 enum _msm_id { MSM8996V3 = 0xF6ul, APQ8096V3 = 0x123ul, MSM8996SG = 0x131ul, APQ8096SG = 0x138ul, }; enum _msm8996_version { MSM8996_V3, MSM8996_SG, NUM_OF_MSM8996_VERSIONS, }; struct qcom_cpufreq_drv; struct qcom_cpufreq_match_data { int (*get_version)(struct device *cpu_dev, struct nvmem_cell *speedbin_nvmem, struct qcom_cpufreq_drv *drv); const char **genpd_names; }; struct qcom_cpufreq_drv { struct opp_table **opp_tables; struct opp_table **genpd_opp_tables; u32 versions; const struct qcom_cpufreq_match_data *data; }; static struct platform_device *cpufreq_dt_pdev, *cpufreq_pdev; static enum _msm8996_version qcom_cpufreq_get_msm_id(void) { size_t len; u32 *msm_id; enum _msm8996_version version; msm_id = qcom_smem_get(QCOM_SMEM_HOST_ANY, MSM_ID_SMEM, &len); if (IS_ERR(msm_id)) return NUM_OF_MSM8996_VERSIONS; /* The first 4 bytes are format, next to them is the actual msm-id */ msm_id++; switch ((enum _msm_id)*msm_id) { case MSM8996V3: case APQ8096V3: version = MSM8996_V3; break; case MSM8996SG: case APQ8096SG: version = MSM8996_SG; break; default: version = NUM_OF_MSM8996_VERSIONS; } return version; } static int qcom_cpufreq_kryo_name_version(struct device *cpu_dev, struct nvmem_cell *speedbin_nvmem, struct qcom_cpufreq_drv *drv) { size_t len; u8 *speedbin; enum _msm8996_version msm8996_version; msm8996_version = qcom_cpufreq_get_msm_id(); if (NUM_OF_MSM8996_VERSIONS == msm8996_version) { dev_err(cpu_dev, "Not Snapdragon 820/821!"); return -ENODEV; } speedbin = nvmem_cell_read(speedbin_nvmem, &len); if (IS_ERR(speedbin)) return PTR_ERR(speedbin); switch (msm8996_version) { case MSM8996_V3: drv->versions = 1 << (unsigned int)(*speedbin); break; case MSM8996_SG: drv->versions = 1 << ((unsigned int)(*speedbin) + 4); break; default: BUG(); break; } kfree(speedbin); return 0; } static const struct qcom_cpufreq_match_data match_data_kryo = { .get_version = qcom_cpufreq_kryo_name_version, }; static const char *qcs404_genpd_names[] = { "cpr", NULL }; static const struct qcom_cpufreq_match_data match_data_qcs404 = { .genpd_names = qcs404_genpd_names, }; static int qcom_cpufreq_probe(struct platform_device *pdev) { struct qcom_cpufreq_drv *drv; struct nvmem_cell *speedbin_nvmem; struct device_node *np; struct device *cpu_dev; unsigned cpu; const struct of_device_id *match; int ret; cpu_dev = get_cpu_device(0); if (!cpu_dev) return -ENODEV; np = dev_pm_opp_of_get_opp_desc_node(cpu_dev); if (!np) return -ENOENT; ret = of_device_is_compatible(np, "operating-points-v2-kryo-cpu"); if (!ret) { of_node_put(np); return -ENOENT; } drv = kzalloc(sizeof(*drv), GFP_KERNEL); if (!drv) return -ENOMEM; match = pdev->dev.platform_data; drv->data = match->data; if (!drv->data) { ret = -ENODEV; goto free_drv; } if (drv->data->get_version) { speedbin_nvmem = of_nvmem_cell_get(np, NULL); if (IS_ERR(speedbin_nvmem)) { if (PTR_ERR(speedbin_nvmem) != -EPROBE_DEFER) dev_err(cpu_dev, "Could not get nvmem cell: %ld\n", PTR_ERR(speedbin_nvmem)); ret = PTR_ERR(speedbin_nvmem); goto free_drv; } ret = drv->data->get_version(cpu_dev, speedbin_nvmem, drv); if (ret) { nvmem_cell_put(speedbin_nvmem); goto free_drv; } nvmem_cell_put(speedbin_nvmem); } of_node_put(np); drv->opp_tables = kcalloc(num_possible_cpus(), sizeof(*drv->opp_tables), GFP_KERNEL); if (!drv->opp_tables) { ret = -ENOMEM; goto free_drv; } drv->genpd_opp_tables = kcalloc(num_possible_cpus(), sizeof(*drv->genpd_opp_tables), GFP_KERNEL); if (!drv->genpd_opp_tables) { ret = -ENOMEM; goto free_opp; } for_each_possible_cpu(cpu) { cpu_dev = get_cpu_device(cpu); if (NULL == cpu_dev) { ret = -ENODEV; goto free_genpd_opp; } if (drv->data->get_version) { drv->opp_tables[cpu] = dev_pm_opp_set_supported_hw(cpu_dev, &drv->versions, 1); if (IS_ERR(drv->opp_tables[cpu])) { ret = PTR_ERR(drv->opp_tables[cpu]); dev_err(cpu_dev, "Failed to set supported hardware\n"); goto free_genpd_opp; } } if (drv->data->genpd_names) { drv->genpd_opp_tables[cpu] = dev_pm_opp_attach_genpd(cpu_dev, drv->data->genpd_names, NULL); if (IS_ERR(drv->genpd_opp_tables[cpu])) { ret = PTR_ERR(drv->genpd_opp_tables[cpu]); if (ret != -EPROBE_DEFER) dev_err(cpu_dev, "Could not attach to pm_domain: %d\n", ret); goto free_genpd_opp; } } } cpufreq_dt_pdev = platform_device_register_simple("cpufreq-dt", -1, NULL, 0); if (!IS_ERR(cpufreq_dt_pdev)) { platform_set_drvdata(pdev, drv); return 0; } ret = PTR_ERR(cpufreq_dt_pdev); dev_err(cpu_dev, "Failed to register platform device\n"); free_genpd_opp: for_each_possible_cpu(cpu) { if (IS_ERR_OR_NULL(drv->genpd_opp_tables[cpu])) break; dev_pm_opp_detach_genpd(drv->genpd_opp_tables[cpu]); } kfree(drv->genpd_opp_tables); free_opp: for_each_possible_cpu(cpu) { if (IS_ERR_OR_NULL(drv->opp_tables[cpu])) break; dev_pm_opp_put_supported_hw(drv->opp_tables[cpu]); } kfree(drv->opp_tables); free_drv: kfree(drv); return ret; } static int qcom_cpufreq_remove(struct platform_device *pdev) { struct qcom_cpufreq_drv *drv = platform_get_drvdata(pdev); unsigned int cpu; platform_device_unregister(cpufreq_dt_pdev); for_each_possible_cpu(cpu) { if (drv->opp_tables[cpu]) dev_pm_opp_put_supported_hw(drv->opp_tables[cpu]); if (drv->genpd_opp_tables[cpu]) dev_pm_opp_detach_genpd(drv->genpd_opp_tables[cpu]); } kfree(drv->opp_tables); kfree(drv->genpd_opp_tables); kfree(drv); return 0; } static struct platform_driver qcom_cpufreq_driver = { .probe = qcom_cpufreq_probe, .remove = qcom_cpufreq_remove, .driver = { .name = "qcom-cpufreq-nvmem", }, }; static const struct of_device_id qcom_cpufreq_match_list[] __initconst = { { .compatible = "qcom,apq8096", .data = &match_data_kryo }, { .compatible = "qcom,msm8996", .data = &match_data_kryo }, { .compatible = "qcom,qcs404", .data = &match_data_qcs404 }, {}, }; /* * Since the driver depends on smem and nvmem drivers, which may * return EPROBE_DEFER, all the real activity is done in the probe, * which may be defered as well. The init here is only registering * the driver and the platform device. */ static int __init qcom_cpufreq_init(void) { struct device_node *np = of_find_node_by_path("/"); const struct of_device_id *match; int ret; if (!np) return -ENODEV; match = of_match_node(qcom_cpufreq_match_list, np); of_node_put(np); if (!match) return -ENODEV; ret = platform_driver_register(&qcom_cpufreq_driver); if (unlikely(ret < 0)) return ret; cpufreq_pdev = platform_device_register_data(NULL, "qcom-cpufreq-nvmem", -1, match, sizeof(*match)); ret = PTR_ERR_OR_ZERO(cpufreq_pdev); if (0 == ret) return 0; platform_driver_unregister(&qcom_cpufreq_driver); return ret; } module_init(qcom_cpufreq_init); static void __exit qcom_cpufreq_exit(void) { platform_device_unregister(cpufreq_pdev); platform_driver_unregister(&qcom_cpufreq_driver); } module_exit(qcom_cpufreq_exit); MODULE_DESCRIPTION("Qualcomm Technologies, Inc. CPUfreq driver"); MODULE_LICENSE("GPL v2"); |