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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 | // SPDX-License-Identifier: GPL-2.0 /* * PLL clock descriptions for TI DA850/OMAP-L138/AM18XX * * Copyright (C) 2018 David Lechner <david@lechnology.com> */ #include <linux/bitops.h> #include <linux/clk-provider.h> #include <linux/clk/davinci.h> #include <linux/clkdev.h> #include <linux/device.h> #include <linux/init.h> #include <linux/io.h> #include <linux/kernel.h> #include <linux/mfd/da8xx-cfgchip.h> #include <linux/mfd/syscon.h> #include <linux/of_address.h> #include <linux/of.h> #include <linux/types.h> #include "pll.h" #define OCSEL_OCSRC_OSCIN 0x14 #define OCSEL_OCSRC_PLL0_SYSCLK(n) (0x16 + (n)) #define OCSEL_OCSRC_PLL1_OBSCLK 0x1e #define OCSEL_OCSRC_PLL1_SYSCLK(n) (0x16 + (n)) static const struct davinci_pll_clk_info da850_pll0_info = { .name = "pll0", .unlock_reg = CFGCHIP(0), .unlock_mask = CFGCHIP0_PLL_MASTER_LOCK, .pllm_mask = GENMASK(4, 0), .pllm_min = 4, .pllm_max = 32, .pllout_min_rate = 300000000, .pllout_max_rate = 600000000, .flags = PLL_HAS_CLKMODE | PLL_HAS_PREDIV | PLL_HAS_POSTDIV | PLL_HAS_EXTCLKSRC, }; /* * NB: Technically, the clocks flagged as SYSCLK_FIXED_DIV are "fixed ratio", * meaning that we could change the divider as long as we keep the correct * ratio between all of the clocks, but we don't support that because there is * currently not a need for it. */ SYSCLK(1, pll0_sysclk1, pll0_pllen, 5, SYSCLK_FIXED_DIV); SYSCLK(2, pll0_sysclk2, pll0_pllen, 5, SYSCLK_FIXED_DIV); SYSCLK(3, pll0_sysclk3, pll0_pllen, 5, 0); SYSCLK(4, pll0_sysclk4, pll0_pllen, 5, SYSCLK_FIXED_DIV); SYSCLK(5, pll0_sysclk5, pll0_pllen, 5, 0); SYSCLK(6, pll0_sysclk6, pll0_pllen, 5, SYSCLK_ARM_RATE | SYSCLK_FIXED_DIV); SYSCLK(7, pll0_sysclk7, pll0_pllen, 5, 0); static const char * const da850_pll0_obsclk_parent_names[] = { "oscin", "pll0_sysclk1", "pll0_sysclk2", "pll0_sysclk3", "pll0_sysclk4", "pll0_sysclk5", "pll0_sysclk6", "pll0_sysclk7", "pll1_obsclk", }; static u32 da850_pll0_obsclk_table[] = { OCSEL_OCSRC_OSCIN, OCSEL_OCSRC_PLL0_SYSCLK(1), OCSEL_OCSRC_PLL0_SYSCLK(2), OCSEL_OCSRC_PLL0_SYSCLK(3), OCSEL_OCSRC_PLL0_SYSCLK(4), OCSEL_OCSRC_PLL0_SYSCLK(5), OCSEL_OCSRC_PLL0_SYSCLK(6), OCSEL_OCSRC_PLL0_SYSCLK(7), OCSEL_OCSRC_PLL1_OBSCLK, }; static const struct davinci_pll_obsclk_info da850_pll0_obsclk_info = { .name = "pll0_obsclk", .parent_names = da850_pll0_obsclk_parent_names, .num_parents = ARRAY_SIZE(da850_pll0_obsclk_parent_names), .table = da850_pll0_obsclk_table, .ocsrc_mask = GENMASK(4, 0), }; int da850_pll0_init(struct device *dev, void __iomem *base, struct regmap *cfgchip) { struct clk *clk; davinci_pll_clk_register(dev, &da850_pll0_info, "ref_clk", base, cfgchip); clk = davinci_pll_sysclk_register(dev, &pll0_sysclk1, base); clk_register_clkdev(clk, "pll0_sysclk1", "da850-psc0"); clk = davinci_pll_sysclk_register(dev, &pll0_sysclk2, base); clk_register_clkdev(clk, "pll0_sysclk2", "da850-psc0"); clk_register_clkdev(clk, "pll0_sysclk2", "da850-psc1"); clk_register_clkdev(clk, "pll0_sysclk2", "da850-async3-clksrc"); clk = davinci_pll_sysclk_register(dev, &pll0_sysclk3, base); clk_register_clkdev(clk, "pll0_sysclk3", "da850-async1-clksrc"); clk = davinci_pll_sysclk_register(dev, &pll0_sysclk4, base); clk_register_clkdev(clk, "pll0_sysclk4", "da850-psc0"); clk_register_clkdev(clk, "pll0_sysclk4", "da850-psc1"); davinci_pll_sysclk_register(dev, &pll0_sysclk5, base); clk = davinci_pll_sysclk_register(dev, &pll0_sysclk6, base); clk_register_clkdev(clk, "pll0_sysclk6", "da850-psc0"); davinci_pll_sysclk_register(dev, &pll0_sysclk7, base); davinci_pll_auxclk_register(dev, "pll0_auxclk", base); clk = clk_register_fixed_factor(dev, "async2", "pll0_auxclk", CLK_IS_CRITICAL, 1, 1); clk_register_clkdev(clk, NULL, "i2c_davinci.1"); clk_register_clkdev(clk, "timer0", NULL); clk_register_clkdev(clk, NULL, "davinci-wdt"); davinci_pll_obsclk_register(dev, &da850_pll0_obsclk_info, base); return 0; } static const struct davinci_pll_sysclk_info *da850_pll0_sysclk_info[] = { &pll0_sysclk1, &pll0_sysclk2, &pll0_sysclk3, &pll0_sysclk4, &pll0_sysclk5, &pll0_sysclk6, &pll0_sysclk7, NULL }; void of_da850_pll0_init(struct device_node *node) { void __iomem *base; struct regmap *cfgchip; base = of_iomap(node, 0); if (!base) { pr_err("%s: ioremap failed\n", __func__); return; } cfgchip = syscon_regmap_lookup_by_compatible("ti,da830-cfgchip"); of_davinci_pll_init(NULL, node, &da850_pll0_info, &da850_pll0_obsclk_info, da850_pll0_sysclk_info, 7, base, cfgchip); } static const struct davinci_pll_clk_info da850_pll1_info = { .name = "pll1", .unlock_reg = CFGCHIP(3), .unlock_mask = CFGCHIP3_PLL1_MASTER_LOCK, .pllm_mask = GENMASK(4, 0), .pllm_min = 4, .pllm_max = 32, .pllout_min_rate = 300000000, .pllout_max_rate = 600000000, .flags = PLL_HAS_POSTDIV, }; SYSCLK(1, pll1_sysclk1, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED); SYSCLK(2, pll1_sysclk2, pll1_pllen, 5, 0); SYSCLK(3, pll1_sysclk3, pll1_pllen, 5, 0); static const char * const da850_pll1_obsclk_parent_names[] = { "oscin", "pll1_sysclk1", "pll1_sysclk2", "pll1_sysclk3", }; static u32 da850_pll1_obsclk_table[] = { OCSEL_OCSRC_OSCIN, OCSEL_OCSRC_PLL1_SYSCLK(1), OCSEL_OCSRC_PLL1_SYSCLK(2), OCSEL_OCSRC_PLL1_SYSCLK(3), }; static const struct davinci_pll_obsclk_info da850_pll1_obsclk_info = { .name = "pll1_obsclk", .parent_names = da850_pll1_obsclk_parent_names, .num_parents = ARRAY_SIZE(da850_pll1_obsclk_parent_names), .table = da850_pll1_obsclk_table, .ocsrc_mask = GENMASK(4, 0), }; int da850_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip) { struct clk *clk; davinci_pll_clk_register(dev, &da850_pll1_info, "oscin", base, cfgchip); davinci_pll_sysclk_register(dev, &pll1_sysclk1, base); clk = davinci_pll_sysclk_register(dev, &pll1_sysclk2, base); clk_register_clkdev(clk, "pll1_sysclk2", "da850-async3-clksrc"); davinci_pll_sysclk_register(dev, &pll1_sysclk3, base); davinci_pll_obsclk_register(dev, &da850_pll1_obsclk_info, base); return 0; } static const struct davinci_pll_sysclk_info *da850_pll1_sysclk_info[] = { &pll1_sysclk1, &pll1_sysclk2, &pll1_sysclk3, NULL }; int of_da850_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip) { return of_davinci_pll_init(dev, dev->of_node, &da850_pll1_info, &da850_pll1_obsclk_info, da850_pll1_sysclk_info, 3, base, cfgchip); } |