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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 | /* SPDX-License-Identifier: GPL-2.0 * * include/asm-sh/spinlock-llsc.h * * Copyright (C) 2002, 2003 Paul Mundt * Copyright (C) 2006, 2007 Akio Idehara */ #ifndef __ASM_SH_SPINLOCK_LLSC_H #define __ASM_SH_SPINLOCK_LLSC_H #include <asm/barrier.h> #include <asm/processor.h> /* * Your basic SMP spinlocks, allowing only a single CPU anywhere */ #define arch_spin_is_locked(x) ((x)->lock <= 0) /* * Simple spin lock operations. There are two variants, one clears IRQ's * on the local processor, one does not. * * We make no fairness assumptions. They have a cost. */ static inline void arch_spin_lock(arch_spinlock_t *lock) { unsigned long tmp; unsigned long oldval; __asm__ __volatile__ ( "1: \n\t" "movli.l @%2, %0 ! arch_spin_lock \n\t" "mov %0, %1 \n\t" "mov #0, %0 \n\t" "movco.l %0, @%2 \n\t" "bf 1b \n\t" "cmp/pl %1 \n\t" "bf 1b \n\t" : "=&z" (tmp), "=&r" (oldval) : "r" (&lock->lock) : "t", "memory" ); } static inline void arch_spin_unlock(arch_spinlock_t *lock) { unsigned long tmp; /* This could be optimised with ARCH_HAS_MMIOWB */ mmiowb(); __asm__ __volatile__ ( "mov #1, %0 ! arch_spin_unlock \n\t" "mov.l %0, @%1 \n\t" : "=&z" (tmp) : "r" (&lock->lock) : "t", "memory" ); } static inline int arch_spin_trylock(arch_spinlock_t *lock) { unsigned long tmp, oldval; __asm__ __volatile__ ( "1: \n\t" "movli.l @%2, %0 ! arch_spin_trylock \n\t" "mov %0, %1 \n\t" "mov #0, %0 \n\t" "movco.l %0, @%2 \n\t" "bf 1b \n\t" "synco \n\t" : "=&z" (tmp), "=&r" (oldval) : "r" (&lock->lock) : "t", "memory" ); return oldval; } /* * Read-write spinlocks, allowing multiple readers but only one writer. * * NOTE! it is quite common to have readers in interrupts but no interrupt * writers. For those circumstances we can "mix" irq-safe locks - any writer * needs to get a irq-safe write-lock, but readers can get non-irqsafe * read-locks. */ static inline void arch_read_lock(arch_rwlock_t *rw) { unsigned long tmp; __asm__ __volatile__ ( "1: \n\t" "movli.l @%1, %0 ! arch_read_lock \n\t" "cmp/pl %0 \n\t" "bf 1b \n\t" "add #-1, %0 \n\t" "movco.l %0, @%1 \n\t" "bf 1b \n\t" : "=&z" (tmp) : "r" (&rw->lock) : "t", "memory" ); } static inline void arch_read_unlock(arch_rwlock_t *rw) { unsigned long tmp; __asm__ __volatile__ ( "1: \n\t" "movli.l @%1, %0 ! arch_read_unlock \n\t" "add #1, %0 \n\t" "movco.l %0, @%1 \n\t" "bf 1b \n\t" : "=&z" (tmp) : "r" (&rw->lock) : "t", "memory" ); } static inline void arch_write_lock(arch_rwlock_t *rw) { unsigned long tmp; __asm__ __volatile__ ( "1: \n\t" "movli.l @%1, %0 ! arch_write_lock \n\t" "cmp/hs %2, %0 \n\t" "bf 1b \n\t" "sub %2, %0 \n\t" "movco.l %0, @%1 \n\t" "bf 1b \n\t" : "=&z" (tmp) : "r" (&rw->lock), "r" (RW_LOCK_BIAS) : "t", "memory" ); } static inline void arch_write_unlock(arch_rwlock_t *rw) { __asm__ __volatile__ ( "mov.l %1, @%0 ! arch_write_unlock \n\t" : : "r" (&rw->lock), "r" (RW_LOCK_BIAS) : "t", "memory" ); } static inline int arch_read_trylock(arch_rwlock_t *rw) { unsigned long tmp, oldval; __asm__ __volatile__ ( "1: \n\t" "movli.l @%2, %0 ! arch_read_trylock \n\t" "mov %0, %1 \n\t" "cmp/pl %0 \n\t" "bf 2f \n\t" "add #-1, %0 \n\t" "movco.l %0, @%2 \n\t" "bf 1b \n\t" "2: \n\t" "synco \n\t" : "=&z" (tmp), "=&r" (oldval) : "r" (&rw->lock) : "t", "memory" ); return (oldval > 0); } static inline int arch_write_trylock(arch_rwlock_t *rw) { unsigned long tmp, oldval; __asm__ __volatile__ ( "1: \n\t" "movli.l @%2, %0 ! arch_write_trylock \n\t" "mov %0, %1 \n\t" "cmp/hs %3, %0 \n\t" "bf 2f \n\t" "sub %3, %0 \n\t" "2: \n\t" "movco.l %0, @%2 \n\t" "bf 1b \n\t" "synco \n\t" : "=&z" (tmp), "=&r" (oldval) : "r" (&rw->lock), "r" (RW_LOCK_BIAS) : "t", "memory" ); return (oldval > (RW_LOCK_BIAS - 1)); } #endif /* __ASM_SH_SPINLOCK_LLSC_H */ |