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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 | /* * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * Copyright (C) 2012-2013 Cavium Inc., All Rights Reserved. * * MD5/SHA1/SHA256/SHA512 instruction definitions added by * Aaro Koskinen <aaro.koskinen@iki.fi>. * */ #ifndef __LINUX_OCTEON_CRYPTO_H #define __LINUX_OCTEON_CRYPTO_H #include <linux/sched.h> #include <asm/mipsregs.h> #define OCTEON_CR_OPCODE_PRIORITY 300 extern unsigned long octeon_crypto_enable(struct octeon_cop2_state *state); extern void octeon_crypto_disable(struct octeon_cop2_state *state, unsigned long flags); /* * Macros needed to implement MD5/SHA1/SHA256: */ /* * The index can be 0-1 (MD5) or 0-2 (SHA1), 0-3 (SHA256). */ #define write_octeon_64bit_hash_dword(value, index) \ do { \ __asm__ __volatile__ ( \ "dmtc2 %[rt],0x0048+" STR(index) \ : \ : [rt] "d" (cpu_to_be64(value))); \ } while (0) /* * The index can be 0-1 (MD5) or 0-2 (SHA1), 0-3 (SHA256). */ #define read_octeon_64bit_hash_dword(index) \ ({ \ u64 __value; \ \ __asm__ __volatile__ ( \ "dmfc2 %[rt],0x0048+" STR(index) \ : [rt] "=d" (__value) \ : ); \ \ be64_to_cpu(__value); \ }) /* * The index can be 0-6. */ #define write_octeon_64bit_block_dword(value, index) \ do { \ __asm__ __volatile__ ( \ "dmtc2 %[rt],0x0040+" STR(index) \ : \ : [rt] "d" (cpu_to_be64(value))); \ } while (0) /* * The value is the final block dword (64-bit). */ #define octeon_md5_start(value) \ do { \ __asm__ __volatile__ ( \ "dmtc2 %[rt],0x4047" \ : \ : [rt] "d" (cpu_to_be64(value))); \ } while (0) /* * The value is the final block dword (64-bit). */ #define octeon_sha1_start(value) \ do { \ __asm__ __volatile__ ( \ "dmtc2 %[rt],0x4057" \ : \ : [rt] "d" (value)); \ } while (0) /* * The value is the final block dword (64-bit). */ #define octeon_sha256_start(value) \ do { \ __asm__ __volatile__ ( \ "dmtc2 %[rt],0x404f" \ : \ : [rt] "d" (value)); \ } while (0) /* * Macros needed to implement SHA512: */ /* * The index can be 0-7. */ #define write_octeon_64bit_hash_sha512(value, index) \ do { \ __asm__ __volatile__ ( \ "dmtc2 %[rt],0x0250+" STR(index) \ : \ : [rt] "d" (value)); \ } while (0) /* * The index can be 0-7. */ #define read_octeon_64bit_hash_sha512(index) \ ({ \ u64 __value; \ \ __asm__ __volatile__ ( \ "dmfc2 %[rt],0x0250+" STR(index) \ : [rt] "=d" (__value) \ : ); \ \ __value; \ }) /* * The index can be 0-14. */ #define write_octeon_64bit_block_sha512(value, index) \ do { \ __asm__ __volatile__ ( \ "dmtc2 %[rt],0x0240+" STR(index) \ : \ : [rt] "d" (value)); \ } while (0) /* * The value is the final block word (64-bit). */ #define octeon_sha512_start(value) \ do { \ __asm__ __volatile__ ( \ "dmtc2 %[rt],0x424f" \ : \ : [rt] "d" (value)); \ } while (0) /* * The value is the final block dword (64-bit). */ #define octeon_sha1_start(value) \ do { \ __asm__ __volatile__ ( \ "dmtc2 %[rt],0x4057" \ : \ : [rt] "d" (value)); \ } while (0) /* * The value is the final block dword (64-bit). */ #define octeon_sha256_start(value) \ do { \ __asm__ __volatile__ ( \ "dmtc2 %[rt],0x404f" \ : \ : [rt] "d" (value)); \ } while (0) /* * Macros needed to implement SHA512: */ /* * The index can be 0-7. */ #define write_octeon_64bit_hash_sha512(value, index) \ do { \ __asm__ __volatile__ ( \ "dmtc2 %[rt],0x0250+" STR(index) \ : \ : [rt] "d" (value)); \ } while (0) /* * The index can be 0-7. */ #define read_octeon_64bit_hash_sha512(index) \ ({ \ u64 __value; \ \ __asm__ __volatile__ ( \ "dmfc2 %[rt],0x0250+" STR(index) \ : [rt] "=d" (__value) \ : ); \ \ __value; \ }) /* * The index can be 0-14. */ #define write_octeon_64bit_block_sha512(value, index) \ do { \ __asm__ __volatile__ ( \ "dmtc2 %[rt],0x0240+" STR(index) \ : \ : [rt] "d" (value)); \ } while (0) /* * The value is the final block word (64-bit). */ #define octeon_sha512_start(value) \ do { \ __asm__ __volatile__ ( \ "dmtc2 %[rt],0x424f" \ : \ : [rt] "d" (value)); \ } while (0) #endif /* __LINUX_OCTEON_CRYPTO_H */ |