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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 | /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (C) 2013 ARM Ltd. */ #ifndef __ASM_PERCPU_H #define __ASM_PERCPU_H #include <linux/preempt.h> #include <asm/alternative.h> #include <asm/cmpxchg.h> #include <asm/stack_pointer.h> static inline void set_my_cpu_offset(unsigned long off) { asm volatile(ALTERNATIVE("msr tpidr_el1, %0", "msr tpidr_el2, %0", ARM64_HAS_VIRT_HOST_EXTN) :: "r" (off) : "memory"); } static inline unsigned long __my_cpu_offset(void) { unsigned long off; /* * We want to allow caching the value, so avoid using volatile and * instead use a fake stack read to hazard against barrier(). */ asm(ALTERNATIVE("mrs %0, tpidr_el1", "mrs %0, tpidr_el2", ARM64_HAS_VIRT_HOST_EXTN) : "=r" (off) : "Q" (*(const unsigned long *)current_stack_pointer)); return off; } #define __my_cpu_offset __my_cpu_offset() #define PERCPU_RW_OPS(sz) \ static inline unsigned long __percpu_read_##sz(void *ptr) \ { \ return READ_ONCE(*(u##sz *)ptr); \ } \ \ static inline void __percpu_write_##sz(void *ptr, unsigned long val) \ { \ WRITE_ONCE(*(u##sz *)ptr, (u##sz)val); \ } #define __PERCPU_OP_CASE(w, sfx, name, sz, op_llsc, op_lse) \ static inline void \ __percpu_##name##_case_##sz(void *ptr, unsigned long val) \ { \ unsigned int loop; \ u##sz tmp; \ \ asm volatile (ARM64_LSE_ATOMIC_INSN( \ /* LL/SC */ \ "1: ldxr" #sfx "\t%" #w "[tmp], %[ptr]\n" \ #op_llsc "\t%" #w "[tmp], %" #w "[tmp], %" #w "[val]\n" \ " stxr" #sfx "\t%w[loop], %" #w "[tmp], %[ptr]\n" \ " cbnz %w[loop], 1b", \ /* LSE atomics */ \ #op_lse "\t%" #w "[val], %[ptr]\n" \ __nops(3)) \ : [loop] "=&r" (loop), [tmp] "=&r" (tmp), \ [ptr] "+Q"(*(u##sz *)ptr) \ : [val] "r" ((u##sz)(val))); \ } #define __PERCPU_RET_OP_CASE(w, sfx, name, sz, op_llsc, op_lse) \ static inline u##sz \ __percpu_##name##_return_case_##sz(void *ptr, unsigned long val) \ { \ unsigned int loop; \ u##sz ret; \ \ asm volatile (ARM64_LSE_ATOMIC_INSN( \ /* LL/SC */ \ "1: ldxr" #sfx "\t%" #w "[ret], %[ptr]\n" \ #op_llsc "\t%" #w "[ret], %" #w "[ret], %" #w "[val]\n" \ " stxr" #sfx "\t%w[loop], %" #w "[ret], %[ptr]\n" \ " cbnz %w[loop], 1b", \ /* LSE atomics */ \ #op_lse "\t%" #w "[val], %" #w "[ret], %[ptr]\n" \ #op_llsc "\t%" #w "[ret], %" #w "[ret], %" #w "[val]\n" \ __nops(2)) \ : [loop] "=&r" (loop), [ret] "=&r" (ret), \ [ptr] "+Q"(*(u##sz *)ptr) \ : [val] "r" ((u##sz)(val))); \ \ return ret; \ } #define PERCPU_OP(name, op_llsc, op_lse) \ __PERCPU_OP_CASE(w, b, name, 8, op_llsc, op_lse) \ __PERCPU_OP_CASE(w, h, name, 16, op_llsc, op_lse) \ __PERCPU_OP_CASE(w, , name, 32, op_llsc, op_lse) \ __PERCPU_OP_CASE( , , name, 64, op_llsc, op_lse) #define PERCPU_RET_OP(name, op_llsc, op_lse) \ __PERCPU_RET_OP_CASE(w, b, name, 8, op_llsc, op_lse) \ __PERCPU_RET_OP_CASE(w, h, name, 16, op_llsc, op_lse) \ __PERCPU_RET_OP_CASE(w, , name, 32, op_llsc, op_lse) \ __PERCPU_RET_OP_CASE( , , name, 64, op_llsc, op_lse) PERCPU_RW_OPS(8) PERCPU_RW_OPS(16) PERCPU_RW_OPS(32) PERCPU_RW_OPS(64) PERCPU_OP(add, add, stadd) PERCPU_OP(andnot, bic, stclr) PERCPU_OP(or, orr, stset) PERCPU_RET_OP(add, add, ldadd) #undef PERCPU_RW_OPS #undef __PERCPU_OP_CASE #undef __PERCPU_RET_OP_CASE #undef PERCPU_OP #undef PERCPU_RET_OP /* * It would be nice to avoid the conditional call into the scheduler when * re-enabling preemption for preemptible kernels, but doing that in a way * which builds inside a module would mean messing directly with the preempt * count. If you do this, peterz and tglx will hunt you down. */ #define this_cpu_cmpxchg_double_8(ptr1, ptr2, o1, o2, n1, n2) \ ({ \ int __ret; \ preempt_disable_notrace(); \ __ret = cmpxchg_double_local( raw_cpu_ptr(&(ptr1)), \ raw_cpu_ptr(&(ptr2)), \ o1, o2, n1, n2); \ preempt_enable_notrace(); \ __ret; \ }) #define _pcp_protect(op, pcp, ...) \ ({ \ preempt_disable_notrace(); \ op(raw_cpu_ptr(&(pcp)), __VA_ARGS__); \ preempt_enable_notrace(); \ }) #define _pcp_protect_return(op, pcp, args...) \ ({ \ typeof(pcp) __retval; \ preempt_disable_notrace(); \ __retval = (typeof(pcp))op(raw_cpu_ptr(&(pcp)), ##args); \ preempt_enable_notrace(); \ __retval; \ }) #define this_cpu_read_1(pcp) \ _pcp_protect_return(__percpu_read_8, pcp) #define this_cpu_read_2(pcp) \ _pcp_protect_return(__percpu_read_16, pcp) #define this_cpu_read_4(pcp) \ _pcp_protect_return(__percpu_read_32, pcp) #define this_cpu_read_8(pcp) \ _pcp_protect_return(__percpu_read_64, pcp) #define this_cpu_write_1(pcp, val) \ _pcp_protect(__percpu_write_8, pcp, (unsigned long)val) #define this_cpu_write_2(pcp, val) \ _pcp_protect(__percpu_write_16, pcp, (unsigned long)val) #define this_cpu_write_4(pcp, val) \ _pcp_protect(__percpu_write_32, pcp, (unsigned long)val) #define this_cpu_write_8(pcp, val) \ _pcp_protect(__percpu_write_64, pcp, (unsigned long)val) #define this_cpu_add_1(pcp, val) \ _pcp_protect(__percpu_add_case_8, pcp, val) #define this_cpu_add_2(pcp, val) \ _pcp_protect(__percpu_add_case_16, pcp, val) #define this_cpu_add_4(pcp, val) \ _pcp_protect(__percpu_add_case_32, pcp, val) #define this_cpu_add_8(pcp, val) \ _pcp_protect(__percpu_add_case_64, pcp, val) #define this_cpu_add_return_1(pcp, val) \ _pcp_protect_return(__percpu_add_return_case_8, pcp, val) #define this_cpu_add_return_2(pcp, val) \ _pcp_protect_return(__percpu_add_return_case_16, pcp, val) #define this_cpu_add_return_4(pcp, val) \ _pcp_protect_return(__percpu_add_return_case_32, pcp, val) #define this_cpu_add_return_8(pcp, val) \ _pcp_protect_return(__percpu_add_return_case_64, pcp, val) #define this_cpu_and_1(pcp, val) \ _pcp_protect(__percpu_andnot_case_8, pcp, ~val) #define this_cpu_and_2(pcp, val) \ _pcp_protect(__percpu_andnot_case_16, pcp, ~val) #define this_cpu_and_4(pcp, val) \ _pcp_protect(__percpu_andnot_case_32, pcp, ~val) #define this_cpu_and_8(pcp, val) \ _pcp_protect(__percpu_andnot_case_64, pcp, ~val) #define this_cpu_or_1(pcp, val) \ _pcp_protect(__percpu_or_case_8, pcp, val) #define this_cpu_or_2(pcp, val) \ _pcp_protect(__percpu_or_case_16, pcp, val) #define this_cpu_or_4(pcp, val) \ _pcp_protect(__percpu_or_case_32, pcp, val) #define this_cpu_or_8(pcp, val) \ _pcp_protect(__percpu_or_case_64, pcp, val) #define this_cpu_xchg_1(pcp, val) \ _pcp_protect_return(xchg_relaxed, pcp, val) #define this_cpu_xchg_2(pcp, val) \ _pcp_protect_return(xchg_relaxed, pcp, val) #define this_cpu_xchg_4(pcp, val) \ _pcp_protect_return(xchg_relaxed, pcp, val) #define this_cpu_xchg_8(pcp, val) \ _pcp_protect_return(xchg_relaxed, pcp, val) #define this_cpu_cmpxchg_1(pcp, o, n) \ _pcp_protect_return(cmpxchg_relaxed, pcp, o, n) #define this_cpu_cmpxchg_2(pcp, o, n) \ _pcp_protect_return(cmpxchg_relaxed, pcp, o, n) #define this_cpu_cmpxchg_4(pcp, o, n) \ _pcp_protect_return(cmpxchg_relaxed, pcp, o, n) #define this_cpu_cmpxchg_8(pcp, o, n) \ _pcp_protect_return(cmpxchg_relaxed, pcp, o, n) #include <asm-generic/percpu.h> #endif /* __ASM_PERCPU_H */ |