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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 | /* SPDX-License-Identifier: GPL-2.0-only */ /* * arch/arm/include/asm/arch_gicv3.h * * Copyright (C) 2015 ARM Ltd. */ #ifndef __ASM_ARCH_GICV3_H #define __ASM_ARCH_GICV3_H #ifndef __ASSEMBLY__ #include <linux/io.h> #include <linux/io-64-nonatomic-lo-hi.h> #include <asm/barrier.h> #include <asm/cacheflush.h> #include <asm/cp15.h> #define ICC_EOIR1 __ACCESS_CP15(c12, 0, c12, 1) #define ICC_DIR __ACCESS_CP15(c12, 0, c11, 1) #define ICC_IAR1 __ACCESS_CP15(c12, 0, c12, 0) #define ICC_SGI1R __ACCESS_CP15_64(0, c12) #define ICC_PMR __ACCESS_CP15(c4, 0, c6, 0) #define ICC_CTLR __ACCESS_CP15(c12, 0, c12, 4) #define ICC_SRE __ACCESS_CP15(c12, 0, c12, 5) #define ICC_IGRPEN1 __ACCESS_CP15(c12, 0, c12, 7) #define ICC_BPR1 __ACCESS_CP15(c12, 0, c12, 3) #define ICC_RPR __ACCESS_CP15(c12, 0, c11, 3) #define __ICC_AP0Rx(x) __ACCESS_CP15(c12, 0, c8, 4 | x) #define ICC_AP0R0 __ICC_AP0Rx(0) #define ICC_AP0R1 __ICC_AP0Rx(1) #define ICC_AP0R2 __ICC_AP0Rx(2) #define ICC_AP0R3 __ICC_AP0Rx(3) #define __ICC_AP1Rx(x) __ACCESS_CP15(c12, 0, c9, x) #define ICC_AP1R0 __ICC_AP1Rx(0) #define ICC_AP1R1 __ICC_AP1Rx(1) #define ICC_AP1R2 __ICC_AP1Rx(2) #define ICC_AP1R3 __ICC_AP1Rx(3) #define ICC_HSRE __ACCESS_CP15(c12, 4, c9, 5) #define ICH_VSEIR __ACCESS_CP15(c12, 4, c9, 4) #define ICH_HCR __ACCESS_CP15(c12, 4, c11, 0) #define ICH_VTR __ACCESS_CP15(c12, 4, c11, 1) #define ICH_MISR __ACCESS_CP15(c12, 4, c11, 2) #define ICH_EISR __ACCESS_CP15(c12, 4, c11, 3) #define ICH_ELRSR __ACCESS_CP15(c12, 4, c11, 5) #define ICH_VMCR __ACCESS_CP15(c12, 4, c11, 7) #define __LR0(x) __ACCESS_CP15(c12, 4, c12, x) #define __LR8(x) __ACCESS_CP15(c12, 4, c13, x) #define ICH_LR0 __LR0(0) #define ICH_LR1 __LR0(1) #define ICH_LR2 __LR0(2) #define ICH_LR3 __LR0(3) #define ICH_LR4 __LR0(4) #define ICH_LR5 __LR0(5) #define ICH_LR6 __LR0(6) #define ICH_LR7 __LR0(7) #define ICH_LR8 __LR8(0) #define ICH_LR9 __LR8(1) #define ICH_LR10 __LR8(2) #define ICH_LR11 __LR8(3) #define ICH_LR12 __LR8(4) #define ICH_LR13 __LR8(5) #define ICH_LR14 __LR8(6) #define ICH_LR15 __LR8(7) /* LR top half */ #define __LRC0(x) __ACCESS_CP15(c12, 4, c14, x) #define __LRC8(x) __ACCESS_CP15(c12, 4, c15, x) #define ICH_LRC0 __LRC0(0) #define ICH_LRC1 __LRC0(1) #define ICH_LRC2 __LRC0(2) #define ICH_LRC3 __LRC0(3) #define ICH_LRC4 __LRC0(4) #define ICH_LRC5 __LRC0(5) #define ICH_LRC6 __LRC0(6) #define ICH_LRC7 __LRC0(7) #define ICH_LRC8 __LRC8(0) #define ICH_LRC9 __LRC8(1) #define ICH_LRC10 __LRC8(2) #define ICH_LRC11 __LRC8(3) #define ICH_LRC12 __LRC8(4) #define ICH_LRC13 __LRC8(5) #define ICH_LRC14 __LRC8(6) #define ICH_LRC15 __LRC8(7) #define __ICH_AP0Rx(x) __ACCESS_CP15(c12, 4, c8, x) #define ICH_AP0R0 __ICH_AP0Rx(0) #define ICH_AP0R1 __ICH_AP0Rx(1) #define ICH_AP0R2 __ICH_AP0Rx(2) #define ICH_AP0R3 __ICH_AP0Rx(3) #define __ICH_AP1Rx(x) __ACCESS_CP15(c12, 4, c9, x) #define ICH_AP1R0 __ICH_AP1Rx(0) #define ICH_AP1R1 __ICH_AP1Rx(1) #define ICH_AP1R2 __ICH_AP1Rx(2) #define ICH_AP1R3 __ICH_AP1Rx(3) /* A32-to-A64 mappings used by VGIC save/restore */ #define CPUIF_MAP(a32, a64) \ static inline void write_ ## a64(u32 val) \ { \ write_sysreg(val, a32); \ } \ static inline u32 read_ ## a64(void) \ { \ return read_sysreg(a32); \ } \ #define CPUIF_MAP_LO_HI(a32lo, a32hi, a64) \ static inline void write_ ## a64(u64 val) \ { \ write_sysreg(lower_32_bits(val), a32lo);\ write_sysreg(upper_32_bits(val), a32hi);\ } \ static inline u64 read_ ## a64(void) \ { \ u64 val = read_sysreg(a32lo); \ \ val |= (u64)read_sysreg(a32hi) << 32; \ \ return val; \ } CPUIF_MAP(ICC_PMR, ICC_PMR_EL1) CPUIF_MAP(ICC_AP0R0, ICC_AP0R0_EL1) CPUIF_MAP(ICC_AP0R1, ICC_AP0R1_EL1) CPUIF_MAP(ICC_AP0R2, ICC_AP0R2_EL1) CPUIF_MAP(ICC_AP0R3, ICC_AP0R3_EL1) CPUIF_MAP(ICC_AP1R0, ICC_AP1R0_EL1) CPUIF_MAP(ICC_AP1R1, ICC_AP1R1_EL1) CPUIF_MAP(ICC_AP1R2, ICC_AP1R2_EL1) CPUIF_MAP(ICC_AP1R3, ICC_AP1R3_EL1) CPUIF_MAP(ICH_HCR, ICH_HCR_EL2) CPUIF_MAP(ICH_VTR, ICH_VTR_EL2) CPUIF_MAP(ICH_MISR, ICH_MISR_EL2) CPUIF_MAP(ICH_EISR, ICH_EISR_EL2) CPUIF_MAP(ICH_ELRSR, ICH_ELRSR_EL2) CPUIF_MAP(ICH_VMCR, ICH_VMCR_EL2) CPUIF_MAP(ICH_AP0R3, ICH_AP0R3_EL2) CPUIF_MAP(ICH_AP0R2, ICH_AP0R2_EL2) CPUIF_MAP(ICH_AP0R1, ICH_AP0R1_EL2) CPUIF_MAP(ICH_AP0R0, ICH_AP0R0_EL2) CPUIF_MAP(ICH_AP1R3, ICH_AP1R3_EL2) CPUIF_MAP(ICH_AP1R2, ICH_AP1R2_EL2) CPUIF_MAP(ICH_AP1R1, ICH_AP1R1_EL2) CPUIF_MAP(ICH_AP1R0, ICH_AP1R0_EL2) CPUIF_MAP(ICC_HSRE, ICC_SRE_EL2) CPUIF_MAP(ICC_SRE, ICC_SRE_EL1) CPUIF_MAP_LO_HI(ICH_LR15, ICH_LRC15, ICH_LR15_EL2) CPUIF_MAP_LO_HI(ICH_LR14, ICH_LRC14, ICH_LR14_EL2) CPUIF_MAP_LO_HI(ICH_LR13, ICH_LRC13, ICH_LR13_EL2) CPUIF_MAP_LO_HI(ICH_LR12, ICH_LRC12, ICH_LR12_EL2) CPUIF_MAP_LO_HI(ICH_LR11, ICH_LRC11, ICH_LR11_EL2) CPUIF_MAP_LO_HI(ICH_LR10, ICH_LRC10, ICH_LR10_EL2) CPUIF_MAP_LO_HI(ICH_LR9, ICH_LRC9, ICH_LR9_EL2) CPUIF_MAP_LO_HI(ICH_LR8, ICH_LRC8, ICH_LR8_EL2) CPUIF_MAP_LO_HI(ICH_LR7, ICH_LRC7, ICH_LR7_EL2) CPUIF_MAP_LO_HI(ICH_LR6, ICH_LRC6, ICH_LR6_EL2) CPUIF_MAP_LO_HI(ICH_LR5, ICH_LRC5, ICH_LR5_EL2) CPUIF_MAP_LO_HI(ICH_LR4, ICH_LRC4, ICH_LR4_EL2) CPUIF_MAP_LO_HI(ICH_LR3, ICH_LRC3, ICH_LR3_EL2) CPUIF_MAP_LO_HI(ICH_LR2, ICH_LRC2, ICH_LR2_EL2) CPUIF_MAP_LO_HI(ICH_LR1, ICH_LRC1, ICH_LR1_EL2) CPUIF_MAP_LO_HI(ICH_LR0, ICH_LRC0, ICH_LR0_EL2) #define read_gicreg(r) read_##r() #define write_gicreg(v, r) write_##r(v) /* Low-level accessors */ static inline void gic_write_eoir(u32 irq) { write_sysreg(irq, ICC_EOIR1); isb(); } static inline void gic_write_dir(u32 val) { write_sysreg(val, ICC_DIR); isb(); } static inline u32 gic_read_iar(void) { u32 irqstat = read_sysreg(ICC_IAR1); dsb(sy); return irqstat; } static inline void gic_write_ctlr(u32 val) { write_sysreg(val, ICC_CTLR); isb(); } static inline u32 gic_read_ctlr(void) { return read_sysreg(ICC_CTLR); } static inline void gic_write_grpen1(u32 val) { write_sysreg(val, ICC_IGRPEN1); isb(); } static inline void gic_write_sgi1r(u64 val) { write_sysreg(val, ICC_SGI1R); } static inline u32 gic_read_sre(void) { return read_sysreg(ICC_SRE); } static inline void gic_write_sre(u32 val) { write_sysreg(val, ICC_SRE); isb(); } static inline void gic_write_bpr1(u32 val) { write_sysreg(val, ICC_BPR1); } static inline u32 gic_read_pmr(void) { return read_sysreg(ICC_PMR); } static inline void gic_write_pmr(u32 val) { write_sysreg(val, ICC_PMR); } static inline u32 gic_read_rpr(void) { return read_sysreg(ICC_RPR); } /* * Even in 32bit systems that use LPAE, there is no guarantee that the I/O * interface provides true 64bit atomic accesses, so using strd/ldrd doesn't * make much sense. * Moreover, 64bit I/O emulation is extremely difficult to implement on * AArch32, since the syndrome register doesn't provide any information for * them. * Consequently, the following IO helpers use 32bit accesses. */ static inline void __gic_writeq_nonatomic(u64 val, volatile void __iomem *addr) { writel_relaxed((u32)val, addr); writel_relaxed((u32)(val >> 32), addr + 4); } static inline u64 __gic_readq_nonatomic(const volatile void __iomem *addr) { u64 val; val = readl_relaxed(addr); val |= (u64)readl_relaxed(addr + 4) << 32; return val; } #define gic_flush_dcache_to_poc(a,l) __cpuc_flush_dcache_area((a), (l)) /* * GICD_IROUTERn, contain the affinity values associated to each interrupt. * The upper-word (aff3) will always be 0, so there is no need for a lock. */ #define gic_write_irouter(v, c) __gic_writeq_nonatomic(v, c) /* * GICR_TYPER is an ID register and doesn't need atomicity. */ #define gic_read_typer(c) __gic_readq_nonatomic(c) /* * GITS_BASER - hi and lo bits may be accessed independently. */ #define gits_read_baser(c) __gic_readq_nonatomic(c) #define gits_write_baser(v, c) __gic_writeq_nonatomic(v, c) /* * GICR_PENDBASER and GICR_PROPBASE are changed with LPIs disabled, so they * won't be being used during any updates and can be changed non-atomically */ #define gicr_read_propbaser(c) __gic_readq_nonatomic(c) #define gicr_write_propbaser(v, c) __gic_writeq_nonatomic(v, c) #define gicr_read_pendbaser(c) __gic_readq_nonatomic(c) #define gicr_write_pendbaser(v, c) __gic_writeq_nonatomic(v, c) /* * GICR_xLPIR - only the lower bits are significant */ #define gic_read_lpir(c) readl_relaxed(c) #define gic_write_lpir(v, c) writel_relaxed(lower_32_bits(v), c) /* * GITS_TYPER is an ID register and doesn't need atomicity. */ #define gits_read_typer(c) __gic_readq_nonatomic(c) /* * GITS_CBASER - hi and lo bits may be accessed independently. */ #define gits_read_cbaser(c) __gic_readq_nonatomic(c) #define gits_write_cbaser(v, c) __gic_writeq_nonatomic(v, c) /* * GITS_CWRITER - hi and lo bits may be accessed independently. */ #define gits_write_cwriter(v, c) __gic_writeq_nonatomic(v, c) /* * GICR_VPROPBASER - hi and lo bits may be accessed independently. */ #define gicr_read_vpropbaser(c) __gic_readq_nonatomic(c) #define gicr_write_vpropbaser(v, c) __gic_writeq_nonatomic(v, c) /* * GICR_VPENDBASER - the Valid bit must be cleared before changing * anything else. */ static inline void gicr_write_vpendbaser(u64 val, void __iomem *addr) { u32 tmp; tmp = readl_relaxed(addr + 4); if (tmp & (GICR_VPENDBASER_Valid >> 32)) { tmp &= ~(GICR_VPENDBASER_Valid >> 32); writel_relaxed(tmp, addr + 4); } /* * Use the fact that __gic_writeq_nonatomic writes the second * half of the 64bit quantity after the first. */ __gic_writeq_nonatomic(val, addr); } #define gicr_read_vpendbaser(c) __gic_readq_nonatomic(c) static inline bool gic_prio_masking_enabled(void) { return false; } static inline void gic_pmr_mask_irqs(void) { /* Should not get called. */ WARN_ON_ONCE(true); } static inline void gic_arch_enable_irqs(void) { /* Should not get called. */ WARN_ON_ONCE(true); } #endif /* !__ASSEMBLY__ */ #endif /* !__ASM_ARCH_GICV3_H */ |